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| November 2006 rev 0.2 ASM2P5T9070A 2.5V Single Data Rate 1:10 Clock Buffer Terabuffer Features * * * * * * * * * * Optimized for 2.5V LVTTL Guaranteed Low Skew < 25pS (max) Very low duty cycle distortion < 300pS (max) High speed propagation delay < 2nS. (max) Up to 200MHz operation Very low CMOS power levels Hot Insertable and over-voltage tolerant inputs 1:10 fanout buffer 2.5V Supply Voltage Available in TSSOP Package The ASM2P5T9070A 2.5V single data rate (SDR) clock buffer is a single-ended input to ten single-ended outputs buffer built on advanced metal CMOS technology. The SDR clock buffer fanout from a single input to ten singleended outputs reduces the loading on the preceding driver and provides an efficient clock distribution network. The ASM2P5T9070A has two output banks that can be asynchronously enabled/disabled. Multiple power and grounds reduce noise. Applications: ASM2P5T9070A is targeted towards Clock and signal distribution applications. Functional Description Block Diagram GL G1 OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL G2 OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL Q1 Q2 Q3 A Q4 Q5 Q6 Q7 Q8 Q9 Q10 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 * Tel: 408-879-9077 * Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. November 2006 rev 0.2 Pin Configuration Top View - TSSOP Package ASM2P5T9070A GL VDD VDD GND GND G1 VDD Q2 Q1 GND VDD GND A VDD GND Q10 Q9 VDD G2 GND GND VDD VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 GND VDD VDD GND GND GND VDD Q3 Q4 GND VDD Q5 Q6 VDD GND Q7 Q8 VDD VDD GND GND VDD GND NC ASM2P5T9070A 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Pin Description Symbol A G1 G2 GL Qn VDD GND NC I/O I I I I O Type LVTTL LVTTL LVTTL LVTTL LVTTL PWR PWR Description Clock input Gate for outputs Q1 through Q5. When G1 is LOW, these outputs are enabled. When G1 is HIGH, these outputs are asynchronously disabled to the level designated by GL1. Gate for outputs Q6through Q10. When G2 is LOW, these outputs are enabled. When G2 is HIGH, these outputs are asynchronously disabled to the level designated by GL1. Specifies output disable level. If HIGH, the outputs disable HIGH. If LOW, the outputs disable LOW. Clock outputs Power supply for the device core, inputs, and outputs Power supply return for power NOTE: Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry. 2.5V Single Data Rate 1:10 Clock Buffer Terabuffer Notice: The information in this document is subject to change without notice. 2 of 9 November 2006 rev 0.2 Absolute Maximum Ratings1 Symbol VDD VI VO TSTG TJ Power Supply Voltage Input Voltage Output Voltage Storage Temperature Junction Temperature ASM2P5T9070A Description Max -0.5 to +3.6 -0.5 to +3.6 -0.5 to VDD +0.5 -65to +165 150 Unit V V V C C Note: 1.These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device reliability. Capacitance1 (TA = +25C, F = 1.0MHz) Symbol CIN Parameter Input Capacitance Min Typ 6 Max Unit pF NOTE: 1. This parameter is measured at characterization but not tested. Recommended Operating Range Symbol TA VDD Description Ambient Operating Temperature Internal Power Supply Voltage Min -40 2.3 Typ +25 2.5 Max +85 2.7 Unit C V DC Electrical Characteristics Over Operating Range1 Symbol IIH IIL VIK VIN VIH VIL VOH VOL Parameter Input HIGH Current Input LOW Current Clamp Diode Voltage DC Input Voltage DC Input HIGH 2 Test Conditions VDD= 2.7V VDD= 2.7V VI = VDD/GND VI = GND/VDD Min Typ4 Max 5 5 Unit A V V V V V V VDD= 2.3V, IIN = -18mA -0.3 1.7 IOH= -12mA IOH= -100A IOL= 12mA IOL= 100A VDD- 0.4 VDD- 0.1 - 0.7 - 1.2 +3.6 0.7 DC Input LOW3 Output HIGH Voltage Output LOW Voltage 0.4 0.1 V V NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. Voltage required to maintain a logic HIGH. 3. Voltage required to maintain a logic LOW. 4. Typical values are at VDD = 2.5V, +25C ambient. 2.5V Single Data Rate 1:10 Clock Buffer Terabuffer Notice: The information in this document is subject to change without notice. 3 of 9 November 2006 rev 0.2 Power Supply Characteristics Symbol IDDQ IDDD ITOT ASM2P5T9070A Parameter Quiescent VDD Power Supply Current Dynamic VDD Power Supply Current per Output Total Power VDD Supply Current Test Conditions1 VDD= Max., Reference Clock = LOW Outputs enabled, All outputs unloaded VDD= Max., VDD= Max., CL= 0pF VDD= 2.5V., FREFERENCE CLOCK= 100MHz, CL= 15pF VDD= 2.5V., FREFERENCE CLOCK= 200MHz, CL= 15pF Typ 1.5 150 70 100 Max 2 200 90 Unit mA A/MHz mA 150 NOTE: 1. The termination resistors are excluded from these measurements. Input AC Test Conditions Symbol VIH VIL VTH tR, tF Input HIGH Voltage Input LOW Voltage Input Timing Measurement Reference Level Input Signal Edge Rate2 1 Parameter Value VDD 0 VDD/2 2 Units V V V V/nS NOTES: 1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment. 2. The input signal edge rate of 2V/nS or greater is to be maintained in the 10% to 90% range of the input waveform. AC Electrical Characteristics Over Operating Range4 Symbol Skew Parameters tSK(O) tSK(P) tSK(PP) tPLH tPHL tR tF fO tPGE tPGD Same Device Output Pin-to-Pin Skew1 Pulse Skew2 Part-to-Part Skew3 25 300 300 pS pS pS Parameter Min Typ Max Unit Propagation Delay Propagation Delay A to Qn Output Rise Time (20% to 80%) Output Fall Time (20% to 80%) Frequency Range Output Gate Enable to Qn Output Gate Enable to Qn Driven to GL Designated Level 350 350 2 850 850 200 3.5 3 nS pS pS MHz nS nS Output Gate Enable/Disable Delay NOTES: 1. Skew measured between all outputs under identical input and output transitions and load conditions on any one device. 2. Skew measured is the difference between propagation delay times tPHL and tPLH of any output under identical input and output transitions and load conditions on any one device. 3. Skew measured is the magnitude of the difference in propagation times between any outputs of two devices, given identical transitions and load conditions at identical VDD levels and temperature. 4. Guaranteed by design. 2.5V Single Data Rate 1:10 Clock Buffer Terabuffer Notice: The information in this document is subject to change without notice. 4 of 9 November 2006 rev 0.2 AC Timing Waveforms ASM2P5T9070A Propagation and Skew Waveforms NOTE: Pulse Skew is calculated using the following expression: tSK(P) = | tPHL - tPLH | where tPHL and tPLH are measured on the controlled edges of any one output from rising and falling edges of a single pulse. Please note that the tPHL and tPLH shown are not valid measurements for this calculation because they are not taken from the same pulse. Gate Disable/Enable Runt Pulse Generation NOTE: As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time their Gx signals to avoid this problem. 2.5V Single Data Rate 1:10 Clock Buffer Terabuffer Notice: The information in this document is subject to change without notice. 5 of 9 November 2006 rev 0.2 Test Circuit and Conditions ASM2P5T9070A Test Circuit for Input/Output Input/Output Test Conditions Symbol VTH R1 R2 CL VDD= 2.5V 0.2V VDD/ 2 100 100 15 Unit V pF 2.5V Single Data Rate 1:10 Clock Buffer Terabuffer Notice: The information in this document is subject to change without notice. 6 of 9 November 2006 rev 0.2 Package Information 48-lead TSSOP (6.10 mm Body, JEDEC MO-153-ED) ASM2P5T9070A Dimensions Symbol Min A A1 A2 b c D E1 E e L N 0 8 0.018 0.004 0.488 0.236 0.319 BSC 0.020 BSC 0.030 48 0 8 0.45 .... 0.002 0.031 0.008 BSC 0.008 0.496 0.244 0.09 12.40 6.00 8.10 BSC 0.50 BSC 0.75 Inches Max 0.047 0.006 0.041 Millimeters Min ... 0.05 0.8 0.20 BSC 0.20 12.60 6.20 Max 1.20 0.15 1.05 2.5V Single Data Rate 1:10 Clock Buffer Terabuffer Notice: The information in this document is subject to change without notice. 7 of 9 November 2006 rev 0.2 Ordering Information Part Number ASM2P5T9070AF-48TT ASM2P5T9070AF-48TR ASM2I5T9070AF-48TT ASM2I5T9070AF-48TR ASM2P5T9070AG-48TT ASM2P5T9070AG-48TR ASM2I5T9070AG-48TT ASM2I5T9070AG-48TR ASM2P5T9070A Marking 2P5T9070AF 2P5T9070AF 2I5T9070AF 2I5T9070AF 2P5T9070AG 2P5T9070AG 2I5T9070AG 2I5T9070AG Package Type 48 Pin TSSOP, Tube, Pb Free 48 Pin TSSOP, Tape and Reel, Pb Free 48 Pin TSSOP, TUBE, Pb Free 48 Pin TSSOP, Tape and Reel, Pb Free 48 Pin TSSOP, Tube, Green 48 Pin TSSOP, Tape and Reel, Green 48 Pin TSSOP, TUBE, Green 48 Pin TSSOP, Tape and Reel, Green Operating Range Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Ordering Information ASM2P5T9070AF-48TR R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 PulseCore Semiconductor Mixed Signal Product Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 2.5V Single Data Rate 1:10 Clock Buffer Terabuffer Notice: The information in this document is subject to change without notice. 8 of 9 November 2006 rev 0.2 ASM2P5T9070A PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright (c) PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: ASM2P5T9070 Document Version: 0.2 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 (c) Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore's best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore's Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore's Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. 2.5V Single Data Rate 1:10 Clock Buffer Terabuffer Notice: The information in this document is subject to change without notice. 9 of 9 |
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